Vidatum - Index

Biography

Brendan Mullane received his BEng. degree in Electronic Engineering from the University of Limerick, Ireland in 1992 and also completed his PhD degree in System-on-Chip Data Converter Built-in-Self-Test in 2010 also from the University of Limerick.

From 1992 to 1995 he worked with Alps Electric (Japan) as a Junior Design Engineer and with LSI Logic (Japan) from 1996 to 2002 as a Senior IC Designer. He is currently a Senior Research Fellow in the Circuits and Systems Research Centre (CSRC) at the University of Limerick, Ireland and has been the principal investigator on a number of significant research projects. He is author of one book chapter and more than 30 articles and holds four patents. His research interests include high performance, low-power VLSI circuits for signal processing, DSP/CPU and data converters (DAC, ADC) applications including digital assist analog IC calibration and Built-in-Self-Test (BIST) research activities. He is also interested in biomedical signal processing for neuroscience applications.

Research Interests

Digital Signal Processing (DSP) and CPU processors, System on Chip (SoC) and VLSI design, Data Converters, Digital Assist Analogue Calibration and DEM Error Correction Techniques, ADC Built-in-Self-Test (BIST), Bio-electronics for Neuroscience.

Book Chapters

�	Year	Publication
	2012	'A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a Low Voltage CMOS Process' Brendan Mullane,Vincent O'Brien (2012) 'A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a Low Voltage CMOS Process' In: VLSI-SoC: Advanced Research for Systems on Chip. Berlin, Germany: Springer. [DOI] [ULIR Link] [Details]

Peer Reviewed Journals

�	Year	Publication
	2020	'High Order Mismatch Shaping for Low Oversampling Rates' O'Brien V.;Mullane B. (2020) 'High Order Mismatch Shaping for Low Oversampling Rates'. Ieee Transactions On Circuits And Systems Ii-Express Briefs, 67 (1):42-46 [DOI] [ULIR Link] [Details]
	2018	'Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs' Danie O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane (2018) 'Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs'. Ieee Transactions On Very Large Scale Integration (Vlsi) Systems, 26 (2):404-415 [DOI] [ULIR Link] [Details]
	2014	'Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics' Bailey C.;Mullane B. (2014) 'Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics'. Vlsi Design, 2014 [DOI] [Details]
	2018	'Performance optimization methods for switched-capacitor biquadratic filters' Nahlik, J;Hospodka, J;Sovka, P;Mullane, B;Subrt, O (2018) 'Performance optimization methods for switched-capacitor biquadratic filters'. Journal Of Electrical Engineering-Elektrotechnicky Casopis, 69 :345-351 [DOI] [Details]
	2017	'A Reduced Hardware ISI and Mismatch Shaping DEM Decoder' Vincent O'Brien, Anthony Scanlan, Brendan Mullane (2017) 'A Reduced Hardware ISI and Mismatch Shaping DEM Decoder'. Circuits Systems And Signal Processing, [DOI] [ULIR Link] [Details]
	2017	'Analysis of feedback predictive encoder based ADCs' Scanlan, Anthony and O'Hare, Daniel and Halton, Mark Keith and O'Brien, Vincent and Mullane, Brendan and Thompson, Eric (2017) 'Analysis of feedback predictive encoder based ADCs'. Compel-The International Journal For Computation And Mathematics In Electrical And Electronic Engineering, 36 (1):129-152 [DOI] [ULIR Link] [Details]
	2010	'Design and implementation challenges for adoption of the IEEE 1500 standard' Higgins, M; MacNamee, C; Mullane, B (2010) 'Design and implementation challenges for adoption of the IEEE 1500 standard'. Iet Computers And Digital Techniques, 4 (1):38-49 [DOI] [Details]

Other Journals

	Year	Publication
	2021	'Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters' Shantanu Mehta, Roberto Pelliconi, Christophe Erdmann, Vincent O'Brien, Brendan Mullane, (2021) 'Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters' IEEE Open Journal of Circuits and Systems, 2 :597-610. [DOI] [Details]
	2020	'Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs' S. Mehta, D. O'Hare, V. O'Brien, E. Thompson, B. Mullane (2020) 'Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs' IEEE Open Journal of Circuits and Systems, 1 :34-47. [DOI] [ULIR Link] [Details]
	2014	'Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics' Christopher Bailey, Brendan Mullane (2014) 'Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics' VLSI Design, Volume 2014 . [DOI] [ULIR Link] [Details]

Conference Publications

	Year	Publication
	2021	*2021 IEEE International Symposium on Circuits and Systems (ISCAS)* Mehta, Shantanu and Mullane, Brendan and O'Brien, Vincent and Pelliconi, Roberto and Erdmann, Christophe (2021) A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters 2021 IEEE International Symposium on Circuits and Systems (ISCAS) , pp.1-5 [DOI] [ULIR Link] [Details]
	2021	*2021 IEEE Biomedical Circuits and Systems Conference (BioCAS)* Fotios Kostarelos, Ciaran MacNamee, Brendan Mullane (2021) A Hardware Implementation of a qEEG-Based Discriminant Function for Brain Injury Detection 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS) [Details]
	2020	*2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS)* S. Mehta, B. Mullane, V. O'Brien, R. Pelliconi and C. Erdmann (2020) A Wideband 6th Order Programmable Bandpass DEM Implementation for a Nyquist DAC 2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , pp.1-4 [DOI] [ULIR Link] [Details]
	2007	*ReSCos2007* Brendan Mullane,Michael Higgins,Ciaran MacNamee,Chen-Huan Chiang,Tapan J Chakraborty,Thomas B Cook (2007) FPGA Prototyping of a Scan Based System-on-Chip Design ReSCos2007 Montpellier, France, [Details]
	2019	*Midwest Symposium on Circuits and Systems* Mullane B.;O'Brien V. (2019) An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test Midwest Symposium on Circuits and Systems , pp.591-594 [DOI] [ULIR Link] [Details]
	2019	*2019 17th IEEE International New Circuits and Systems Conference (NEWCAS)* Shantanu Mehta ; Anthony G. Scanlan ; Brendan Mullane ; Daniel O'Hare (2019) A Tri-level Current-Steering DAC Design with Improved Output-Impedance Related Dynamic Performance 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS) Munich, Germany, [DOI] [ULIR Link] [Details]
	2018	*IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)* Brendan Mullane, Vincent O'Brien (2018) An in-place processor design for real-value FFTs targeting in-situ dynamic ADC test IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) [ULIR Link] [Details]
	2014	*25th IET Irish Signals & Systems Conference 2014 and 2014 China-Ireland International Conference on Information and Communications Technologies (ISSC 2014/CIICT 2014)* O'Brien, V.; MacNamee, C.; Mullane, B. (2014) High Order Dynamic Element Matching for multi-bit Delta Sigma A/D & D/A converters 25th IET Irish Signals & Systems Conference 2014 and 2014 China-Ireland International Conference on Information and Communications Technologies (ISSC 2014/CIICT 2014) Limerick, Ireland, , pp.418-423 [DOI] [Details]
	2014	*IET Conference Publications* O'Brien V.;MacNamee C.;Mullane B. (2014) High order dynamic element matching for multibit delta sigma A/D & D/A converters IET Conference Publications , pp.418-423 [DOI] [Details]
	2014	*IET Conference Publications* Nahlik J.;Mullane B.;Hospodka J.;Sovka P.;O'Hare D. (2014) Optimized switched capacitor biquads for two-channel quadrature-mirror filter bank IET Conference Publications , pp.412-417 [DOI] [Details]
	2014	*25th IET Irish Signals & Systems Conference 2014 and 2014 China-Ireland International Conference on Information and Communications Technologies (ISSC 2014/CIICT 2014)* Nahlik, J.; Mullane, B.; Hospodka, J.; Sovka, P.; O'Hare, D (2014) Optimized switched capacitor biquads for two-channel quadrature-mirror filter bank 25th IET Irish Signals & Systems Conference 2014 and 2014 China-Ireland International Conference on Information and Communications Technologies (ISSC 2014/CIICT 2014) Limerick, [DOI] [Details]
	2013	*IEEE European Conference on Circuit Theory and Design, (ECCTD)* Hongjia Mo, Michael Peter Kennedy, Vincent O'Brien, Brendan Mullane (2013) Experimental validation of DAC with nested bus-splitting EFM4 DDSM . In: IEEE eds. IEEE European Conference on Circuit Theory and Design, (ECCTD) Dresden, [DOI] [Details]
	2013	*2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings* Mo H.;Kennedy M.;O'Brien V.;Mullane B. (2013) Experimental validation of DAC with nested bus-splitting EFM4 DDSM 2013 European Conference on Circuit Theory and Design, ECCTD 2013 - Proceedings [Details]
	2012	*IFIP Advances in Information and Communication Technology* Mullane B.;O'Brien V. (2012) A 100dB SFDR 0.5V pk-pk band-pass DAC implemented on a low voltage CMOS process IFIP Advances in Information and Communication Technology , pp.144-157 [DOI] [Details]
	2011	*IEEE International Conference on Electronics, Circuits and Systems, (ICECS)* O'Brien, V.; Mullane, B (2011) High order mismatch noise shaping for bandpass DACs . In: IEEE eds. IEEE International Conference on Electronics, Circuits and Systems, (ICECS) [DOI] [Details]
	2011	*IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)* Mullane, Brendan,O'Brien, Vincent (2011) A high performance band-pass DAC architecture and design targeting a low voltage silicon process . In: IEEE eds. IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC) Hong Kong, [DOI] [Details]
	2010	*ECSI-2010 Silicon for Debug (S4D)* Mullane, Brendan,O'Brien, Vincent,MacNamee, Ciaran,Laumer, Michael (2010) A Reusable On-Chip Built-In-Self-Test Platform for Analog to Digital Converters Targeting In-Situ Device, Test, Debug and Analysis ECSI-2010 Silicon for Debug (S4D) [Details]
	2009	*Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLVLSI)* Brendan Mullane, Ciaran MacNamee, Vincent O'Brien, Thomas Flesichmann (2009) An On-Chip Solution for Static ADC Test and Measurement Proceedings of the 19th ACM Great Lakes symposium on VLSI (GLVLSI) Boston, MA, USA, [DOI] [Details]
	2009	*IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS)* Mullane, B; OBrien, V; MacNamee, C; Fleischmann, T (2009) An SOC Platform for ADC Test and Measurement IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS) , pp.4-7 [Details]
	2009	*IEEE European Test Symposium, (ETS)* Mullane B., MacNamee C., O'Brien V., and Fleischmann T. (2009) A Low Cost On-Chip Design Platform for Static ADC Measurments IEEE European Test Symposium, (ETS) [Details]
	2009	*International Test Conference, (ITC)* Mullane B., O'Brien V., MacNamee C., Fleischmann T. (2009) A2DTest: A complete integrated solution for on-chip ADC self-test and analysis International Test Conference, (ITC) [DOI] [Details]
	2009	*Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009* Mullane B., O'Brien V., MacNamee C., Fleischmann T. (2009) An SOC platform for ADC test and measurement Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009 , pp.4-7 [DOI] [Details]
	2009	*IEEE International SOC Conference, (SOCC)* Mullane B., O'Brien V., MacNamee C., Fleischmann T. (2009) A prototype platform for system-on-chip ADC test and measurement IEEE International SOC Conference, (SOCC) , pp.169-172 [DOI] [Details]
	2008	*Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008* Higgins M., MacNamee C., Mullane B. (2008) A novel system on chip (SoC) test solution Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 , pp.145-150 [DOI] [Details]
	2008	*PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS* Fleischmann, T; Mullane, B (2008) A Dynamic ADC Test Processor for Built-in-Self-Test of ADCs PROCEEDINGS OF THE 12TH WSEAS INTERNATIONAL CONFERENCE ON CIRCUITS , pp.456-461 [Details]
	2008	*2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS* Higgins, M; MacNamee, C; Mullane, B (2008) SoCECT: System on Chip Embedded Core Test 2008 IEEE WORKSHOP ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, PROCEEDINGS , pp.326-331 [Details]
	2008	*Proceedings - International Test Conference* Mullane B.;Higgins M.;MacNamee C. (2008) IEEE 1500 core wrapper optimization techniques and implementation Proceedings - International Test Conference [DOI] [Details]
	2008	*2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS* Mullane, B; Higgins, M; MacNamee, C (2008) IEEE 1500 Core Wrapper Optimization Techniques and Implementation 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS , pp.747-756 [Details]
	2008	*IET Conference Publications* Mullane B., Higgins M., MacNamee C. (2008) An optimal IEEE 1500 core wrapper design for improved test access and reduced test time IET Conference Publications , pp.204-209 [DOI] [Details]
	2008	*DDECS2008 - Workshop on Design and Diagnostics of Electronic Systems* Michael Higgins,Ciaran MacNamee,Brendan Mullane (2008) SoCECT: System on Chip Embedded Core Test DDECS2008 - Workshop on Design and Diagnostics of Electronic Systems Slovakia, [Details]
	2008	*IET Conference Publications* Higgins M., MacNamee C., Mullane B. (2008) IEEE 1500 wrapper control using an IEEE 1149.1 test access port IET Conference Publications , pp.198-203 [DOI] [Details]
	2007	*IT&T2007* Michael Higgins,Ciaran Macnamee,Brendan Mullane (2007) Optimisation and Control of IEEE 1500 Wrappers and User Defined TAMs IT&T2007 Blanchardstown, Dublin, [Details]
	2007	*NATW2007* Michael Higgins,Ciaran Macnamee,Brendan Mullane (2007) Optimisation of IEEE 1500 Wrappers and User Defined TAMs NATW2007 Boston, [Details]
	2006	*IPSOC2006* Mullane, Brendan,MacNamee, Ciaran (2006) Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment IPSOC2006 Grenoble France, [Details]

Published Reports

	Year	Publication
	2002	High Performance Processor IP and AMBA Core Infrastructure. Brendan Mullane (2002) High Performance Processor IP and AMBA Core Infrastructure. ARM Developer's Guide, Toyko, JapanARM Developer's Guide, Toyko, Japan, . [Details]
	2002	High Performance Processor IP and AMBA Core Infrastructure. Brendan Mullane (2002) High Performance Processor IP and AMBA Core Infrastructure. ARM Developer's Guide, Toyko, JapanARM Developer's Guide, Toyko, Japan, . [Details]
	2004	An ASIC primer - Everything you ever wanted to know about ASICs but were afraid to ask. Alan Dunne,Brendan Mullane ,John Kelly,Gerard Kennedy (2004) An ASIC primer - Everything you ever wanted to know about ASICs but were afraid to ask. Shannon Development TechwatchShannon Development Techwatch, . [Details]

Conference Paper

	Year	Publication
	2007	FPGA PROTOTYPING OF A SCAN BASED SYSTEM-ON-CHIP DESIGN. Mullane, B; Higgins, M; MacNamee, C; Chen-Huan Chiang; Chakraborty, TJ; Cook, TB (2007) FPGA PROTOTYPING OF A SCAN BASED SYSTEM-ON-CHIP DESIGN. Montpellier: Conference Paper [Details]
	2008	An Optimal IEEE 1500 Core Wrapper Design for Improved Test Access and Reduced Test Time. 16th IET Irish Signals and Systems Conference. Brendan Mullane,Michael Higgins,Ciaran MacNamee (2008) An Optimal IEEE 1500 Core Wrapper Design for Improved Test Access and Reduced Test Time. 16th IET Irish Signals and Systems Conference. UCG Galway, IrelandUCG Galway, Ireland: Conference Paper [Details]
	2008	IEEE 1500 Wrapper Control using an IEEE 1149.1. Test Access Port. 16th IET Irish Signals and Systems Conference. Michael Higgins,Brendan Mullane,Ciaran MacNamee (2008) IEEE 1500 Wrapper Control using an IEEE 1149.1. Test Access Port. 16th IET Irish Signals and Systems Conference. UCG Galway, IrelandUCG Galway, Ireland: Conference Paper [Details]
	2009	A High Precision Analog Signal Generator Design for ADC BIST. European Test Symposium, 2009. ETS '09. 14th IEEE. O'Brien, Vincent,Mullane, Brendan,Fleischmann, Thomas,MacNamee, Ciaran (2009) A High Precision Analog Signal Generator Design for ADC BIST. European Test Symposium, 2009. ETS '09. 14th IEEE. Conference Paper [Details]
	2009	A Low Cost On-Chip Design Platform for Static ADC Measurments. European Test Symposium, 2009. ETS '09. 14th IEEE. Mullane, Brendan,MacNamee, Ciaran,O'Brien, Vincent,Fleischmann, Thomas (2009) A Low Cost On-Chip Design Platform for Static ADC Measurments. European Test Symposium, 2009. ETS '09. 14th IEEE. Conference Paper [Details]

Magazine Article

	Year	Publication
	2007	Developing a Reusable IP Platform for a System-on-Chip Design Framework. KIPEX Monthly Magazine. Mullane, Brendan,MacNamee, Ciaran (2007) Developing a Reusable IP Platform for a System-on-Chip Design Framework. KIPEX Monthly Magazine. KoreaKorea: Magazine Article [Details]

Thesis

	Year	Publication
	2006	Establishing a Platform for the Development of Reusable IP within a System-on-Chip Design Framework. Mullane, B (2006) Establishing a Platform for the Development of Reusable IP within a System-on-Chip Design Framework. Universityof Limerick: Thesis [Details]
	2009	An On-Chip Test System for Dynamic ADC Parameters. Thomas Fleischmann (2009) An On-Chip Test System for Dynamic ADC Parameters. Thesis [Details]

Translation

	Year	Publication
	2007	Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment. Mullane, B; MacNamee, C (2007) Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment. Translation [Details]

Workshops

	Year	Publication
	2007	Optimisation of IEEE 1500 Wrappers and User Defined TAMs. Higgins, M; Macnamee, C; Mullane, B (2007) Optimisation of IEEE 1500 Wrappers and User Defined TAMs. Boxborough, MA, USA: Workshops [Details]
	2007	Optimisation and Control of IEEE 1500 Wrappers and User Defined TAMs. Higgins, M; MacNamee, C; Mullane, B (2007) Optimisation and Control of IEEE 1500 Wrappers and User Defined TAMs. Blanchardstown: Workshops [Details]

Conference Presentation

	Year	Publication
	2006	Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment. Mullane, B; MacNamee, C (2006) Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment. Grenoble, France: Conference Presentation [Details]

Correction

	Year	Publication
	2018	A Reduced Hardware ISI and Mismatch Shaping DEM Decoder (vol 37, pg 2229, 2018). O'Brien, V;Scanlan, AG;Mullane, B (2018) A Reduced Hardware ISI and Mismatch Shaping DEM Decoder (vol 37, pg 2229, 2018). NEW YORK: Correction [DOI] [Details]

Generic

	Year	Publication
	2004	Digital Issues in Mixed Signal ASIC Design. Brendan Mullane (2004) Digital Issues in Mixed Signal ASIC Design. Generic [Details]

Other Items Published

	Year	Publication
	2001	AMBA SoC and ARM IP Infrastructure. Mullane, B (2001) AMBA SoC and ARM IP Infrastructure. Other Items Published [Details]
	2004	Technology Transfer Initiative. Mullane, B; Scanlan, T; Kelly, JB; Kennedy, G (2004) Technology Transfer Initiative. Other Items Published [Details]
	2004	An ASIC Primer. Dunne, A; kelly, JB; Mullane, B; Kennedy, G (2004) An ASIC Primer. Other Items Published [Details]

Professional Associations

	Association	Function	From / To
	IEEE - Advancing Technology for Humanity	member	01-JAN-06 /

Patents

Patent Number	Title	Inventor	Granted
US 9762258 B2	Mismatch and inter symbol interference (ISI) shaping using dynamic element matching	Vincent O'brien, Brendan Mullane, Tony Scanlan	12-SEP-17
US8386209 B2	Testing system	Brendan Mullane, Thomas Fleischmann, Vincent O'brien	26-FEB-13
US 6782366 B1	Method for independent dynamic range control	Wen Huang, Winnie K. W. Lau, Brendan J. Mullane	24-AUG-04
US6785655 B1	Method for independent dynamic range control	Wen Huang, Winnie K. W. Lau, Brendan J. Mullane	31-AUG-04

Committees

	Committee	Function	From / To
	ISSC Program Committee	The Programme Committee will select high quality papers containing original work. The Programme Committee encourages submissions that include implementation or simulation aspects, along with theoretical analysis and design. There will be prizes for the best paper and the best poster presented at the conference.	2013 / 2016
	MIDAS - Microlectrionics Industry Association Ireland	Training Committe member	2011 / 2013

Employment

Employer	Position	From / To
LSI Logic, Japan	Snr. IC Design Engineer	01-OCT-96 / 01-JUL-03
Silicon Systems Design Ltd.	Snr. Design Enginner	05-APR-95 / 01-SEP-96
ALPS Electric Co, Japan	Design Engineer	01-OCT-92 / 01-APR-95

Education

Year	Institution	Qualification	Subject
2011	University of Limerick	PhD	A Programmable Design for Test Platform for Mixed-Signal System-on-Chip Analog to Digital Converter Applications
2006	University of Limerick	Masters by research	Establishing a Platform for the Development of Reusable IP within a System-On-Chip Design Framework
1992	University of Limerick	B.Eng.

Languages

	Language	Reading	Writing	Speaking
	Japanese	Functional	Basic	Fluent

Outreach Activities

	Description
	Select Topics in Data Converters Workshop organizer (2015~)
	Microelectronics Industry Association - Training Comittee member 2011~2013

Recent Postgraduates

Graduation	Student Name	University	Degree	Thesis
2018	Daniel O Hare	University of Limerick	Doctor of Philosophy	Design of continuous time input pipelined ADCs for advanced cmos technologies
2021	Fotios Kostarelos	University of Limerick	Master of Engineering	A Hardware Implementation of a qEEG-based Discriminant Function for Brain Injury Detection
2021	Shantanu Mehta	University of Limerick	Doctor of Philosophy	Nyquist-rate Current-Steering D/A Converters - Error Analysis, Modelling and Mitigation Techniques.
2020	James Macasaet	University of Limerick	Master of Engineering	A SINGLE POWER SUPPLY SOLUTION FOR DUAL-SUPPLY DIGITAL-TO-ANALOG CONVERTER SYSTEMS
2017	Venkatesh Karra	University of Limerick	Master of Engineering	A FPGA Test Platform for Data Converters
2018	Vincent O Brien	University of Limerick	Doctor of Philosophy	Design of high order mismatch and ISI shaping dynamic element matching decoders for delta sigma data converters

Modules Taught

Term (ID))	Title	Link	Subject
1/2021	Digital Signal Processing 1	CE4817	Digital Signal Processing
2/2013	ASICS2	EE6622	CMOS Analog IC Design
1/2020	Digital Signal Processing 1	CE4817	DSP
1/2019	Digital Signal Processing	EE6451	Signal processing, sampling, aliasing, quantization, DFT/FFT, Digital filters
1/2019	Digital Signal Processing 1	CE4817	Signal processing, sampling, aliasing, quantization, DFT/FFT, Digital filters