This paper presents a solution for implementing low-cost ADC BIST into a
System-on-Chip design. The solution is based on generating a
programmable ramp as a test signal into the ADC and measuring the linear
parameters using the histogram based test. An original approach for
accurately measuring the Flits-per-Code as the ramp traverses the ADC
transfer curve is presented. In particular, it is shown that code
transitions or code flicker noise have an impact on the overall
accuracy. This test procedure permits a ramp generator implementation
and test engine design that is predominantly a digital solution. Results
demonstrate lower silicon area overheads and lower test time
capability.