Mullane, Brendan,O'Brien, Vincent

IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)

A high performance band-pass DAC architecture and design targeting a low voltage silicon process

2011

October

Published

1

()

DSDS, DAC, curent-steering, SFDR, DEM

IEEE

Hong Kong

Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance band-pass DAC architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power DAC is portable to standard CMOS processes and achieves 110dB narrowband SFDR performance using sigma-delta (
) modulation and multi-bit current steering techniques. A 3rd order digital
 modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch
variations. A low silicon area output stage is used to deliver a high performance specification

http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6081601&isnumber=6081592

10.1109/VLSISoC.2011.6081601