Rao, M,Newe, T,Grout, I,Mathur, A

2016

July

Journal Of Circuits Systems And Computers

High Speed Implementation of a SHA-3 Core on Virtex-5 and Virtex-6 FPGAs

Published

()

Cryptography SHA-3 FPGA high-speed architecture LUT BITW VPN

25

This work presents a novel technique for a high-speed implementation of the newly selected cryptographic hash function, Secure Hash Algorithm-3 (SHA-3) on Xilinx's Virtex-5 and Virtex-6 Field Programmable Gate Arrays (FPGAs). The proposed technique consists of a two-phase implementation approach. In the first phase, all steps of the SHA-3 core are logically combined, which helps to eliminate the intermediate states of core function, these states utilize more area and also slow the execution. The second phase deals with the hardware implementation of the first phase equations using Xilinx Look-Up-Table (LUT) primitives. This two phase implementation technique results in a throughput of 19.241 Gbps on a Virtex-6 FPGA; this is the highest reported throughput to date for an FPGA implementation of SHA-3. This high throughput makes this technique ideally suited for the provision of Bump In The Wire (BITW) security for Internet of Things (IoT) applications.

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84960435952&partnerID=40&md5=aa8cab1a1f03b0ffdceb878902c6c700

10.1142/S0218126616500699