In the field of safety-critical applications, the industry has seen a dramatic increase in system integration and complexity for on-chip solutions, and this provides new challenges in gaining deep testability access within such products. IC developers have responded to this challenge by creating sophisticated on-chip trace/test/debug modules to facilitate real-time access to application programs' features in deeply embedded pipeline and cache based architectures for embedded-core-based chips. However, the emerging safety requirements for complex systems demand more stringent solutions for confirming confidence in systems and this leads to a requirement for the formal verification of some key system properties. In this paper the authors propose that the existing architectures for on-chip trace/test/debug modules can be extended to support runtime verification monitoring, working towards the formal verification of system properties of interest. A real benefit in the proposed solution is the provision of a lifecycle use for the on-chip debug logic, thus offering an improved return-on-investment prospect by justifying the resident logic with the benefit gained by lifelong runtime verification features.