Peer-Reviewed Journal Details
Mandatory Fields
Vincent O'Brien, Anthony Scanlan, Brendan Mullane
2017
October
Circuits Systems And Signal Processing
A Reduced Hardware ISI and Mismatch Shaping DEM Decoder
Published
3 ()
Optional Fields
Delta sigma Digital-to-analog converter (DAC) Dynamic element matching (DEM) Element selection logic (ESL) Intersymbol interference (ISI)
This paper presents a dynamic element matching (DEM) decoder incorporating both intersymbol interference (ISI) and mismatch error shaping. From the analysis of ISI error in multi-bit DACs, an algorithm is developed that deterministically controls the element transitions, such that on each conversion cycle the instantaneous number of on transitions is set to a constant value, while the instantaneous number of off transitions varies with the decoder input signal. The technique achieves greater ISI error mitigation than previous approaches using less hardware. To further reduce the logic area, a hierarchical DEM structure, whereby the DEM decoder is split into multiple sub-DEM decoders, is presented.
1531-5878
https://link.springer.com/article/10.1007/s00034-017-0681-8
10.1007/s00034-017-0681-8
Grant Details
This work has been supported by Enterprise Ireland, Innovation Partnership Project IP/2013/0271 co-funded by the Irish Government and the EU European Regional Development Fund (ERDF).