Danie O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane

2018

February

Ieee Transactions On Very Large Scale Integration (Vlsi) Systems

Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs

Published

()

Analog-to-digital conversion antialias filter CMOS analog integrated circuits continuous time (CT) pipeline delays Bandwidth Estimation Capacitors Clocks Pipelines Switches

26

2

404

415

This paper presents design analysis and insights for a new continuous-time input pipeline (CTIP) analog-to-digital converter (ADC) architecture that has enhanced bandwidth. An all-pass filter-based analog delay in the signal path allows bandwidth extension to Nyquist signal bandwidths. A resetting integrator gain stage provides a signal path delay helping to increase the bandwidth while reducing the power cost. The noise filtering property of the resetting integrator gain stage preserves the medium resistive input benefit of CTIP ADCs. The resetting integrator allows the architecture to be implemented with a feedforward compensated op-amp using low-voltage CMOS processes. This paper has been verified by simulation results of a CTIP ADC with 1.2-V supply voltage designed in TSMC's 65-nm CMOS technology.

IEEE

http://ieeexplore.ieee.org/document/8091299/

10.1109/TVLSI.2017.2763129

Enterprise Ireland, Innovation Partnership Project IP-2014- 0293