Peer-Reviewed Journal Details
Mandatory Fields
Rao, M;Newe, T;Omerdic, E;Dooly, G;Lewis, E;Toal, D
2018
January
International Journal Of Internet Protocol Technology
An efficient implementation of FPGA based high speed IPSec (AH/ESP) core
Published
1 ()
Optional Fields
IOT
11
97
109
The IPSec is used to secure the IP traffic. The IPSec protocol was designed to fulfil the need to provide security at the network level, so that all the higher-layer protocols in the OSI model could take advantage of it. The implementation of IPSec is a computationally heavy task that affects the high speed network performance. To overcome this issue, the best possible solution is hardware implementation. For a hardware implementation the FPGA platform is considered as one of the best solutions because of its re-configurability and high performance capabilities. The work presented here gives a complete FPGA based implementation of IPSec. This includes both (AH and ESP) IPSec protocol formats. Both IPSec formats are implemented using transport mode and tunnel mode operations. IPSec is not bounded to use any specific cryptographic algorithms; here IPSec is used with the AES and SHA-3 algorithms to provide confidentiality and integrity services respectively.
GENEVA
1743-8209
10.1504/IJIPT.2018.10013699
Grant Details