Mullane B.;Higgins M.;MacNamee C.

Proceedings - International Test Conference

IEEE 1500 core wrapper optimization techniques and implementation

2008

December

Published

1

()

IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated. © 2008 IEEE.

10.1109/TEST.2008.4700629