Tri-level,Current-Steering,DAC,SFDR,
HD3
This paper presents a design of a low-latency 12-bit linear tri-level current-steering digital-to-analogue-converter for use in continuous-time ADCs. The DAC design achieves 12-bit static linearity, while the combination of DAC slice impedance matching with a proposed compensation technique reduces output-impedance related distortion. The technique demonstrates ~10dB improvement in DAC dynamic performance at high frequencies over the Nyquist-band at 100MS/s. The DAC has been verified by simulation results in TSMC 1.2V 65nm CMOS technology.